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use alloc::string::String;
use alloc::vec;
use alloc::vec::Vec;
use alloc::sync::Arc;
use core::ptr::{read_volatile, write_volatile};
use crate::scheme::{BlockScheme, Scheme};
use crate::DeviceResult;
use lock::Mutex;
use super::nvme_queue::*;
pub struct NvmeInterface {
name: String,
admin_queue: Arc<Mutex<NvmeQueue<ProviderImpl>>>,
io_queues: Vec<Arc<Mutex<NvmeQueue<ProviderImpl>>>>,
bar: usize,
irq: usize,
}
impl NvmeInterface {
pub fn new(bar: usize, irq: usize) -> DeviceResult<NvmeInterface> {
let admin_queue = Arc::new(Mutex::new(NvmeQueue::new(0, 0)));
let io_queues = vec![Arc::new(Mutex::new(NvmeQueue::<ProviderImpl>::new(1, 0x8)))];
let mut interface = NvmeInterface {
name: String::from("nvme"),
admin_queue,
io_queues,
bar,
irq,
};
interface.init();
Ok(interface)
}
pub fn init(&mut self) {
self.nvme_configure_admin_queue();
self.nvme_alloc_io_queue();
}
pub fn get_name_irq(&self) -> (String, usize) {
(self.name.clone(), self.irq)
}
}
impl NvmeInterface {
pub fn nvme_configure_admin_queue(&mut self) {
let mut admin_queue = self.admin_queue.lock();
let bar = self.bar;
let dbs = bar + NVME_REG_DBS;
let sq_dma_pa = admin_queue.sq_pa as u32;
let cq_dma_pa = admin_queue.cq_pa as u32;
let data_dma_pa = admin_queue.data_pa as u64;
let aqa_low_16 = 31_u16;
let aqa_high_16 = 31_u16;
let aqa = (aqa_high_16 as u32) << 16 | aqa_low_16 as u32;
let aqa_address = bar + NVME_REG_AQA;
unsafe {
write_volatile(aqa_address as *mut u32, aqa);
}
let asq_address = bar + NVME_REG_ASQ;
unsafe {
write_volatile(asq_address as *mut u32, sq_dma_pa);
}
let acq_address = bar + NVME_REG_ACQ;
unsafe {
write_volatile(acq_address as *mut u32, cq_dma_pa);
}
let mut ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
ctrl_config |= 0 << NVME_CC_MPS_SHIFT;
ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
unsafe { write_volatile((bar + NVME_REG_CC) as *mut u32, ctrl_config) }
let _dev_status = unsafe { read_volatile((bar + NVME_REG_CSTS) as *mut u32) };
let mut cmd = NvmeIdentify::new();
cmd.prp1 = data_dma_pa;
cmd.command_id = 0x1018;
cmd.nsid = 1;
let common_cmd = unsafe { core::mem::transmute(cmd) };
admin_queue.sq[0].write(common_cmd);
admin_queue.sq_tail += 1;
let admin_q_db = dbs + admin_queue.db_offset;
unsafe { write_volatile(admin_q_db as *mut u32, 1) }
loop {
let status = admin_queue.cq[0].read();
if status.status != 0 {
unsafe { write_volatile((admin_q_db + 0x4) as *mut u32, 1) }
break;
}
}
}
pub fn nvme_alloc_io_queue(&mut self) {
let mut admin_queue = self.admin_queue.lock();
let bar = self.bar;
let dev_dbs = bar + NVME_REG_DBS;
let admin_q_db = dev_dbs;
let mut cmd = NvmeCommonCommand::new();
cmd.opcode = 0x09;
cmd.command_id = 0x2;
cmd.nsid = 1;
cmd.cdw10 = 0x7;
admin_queue.sq[1].write(cmd);
admin_queue.sq_tail += 1;
unsafe { write_volatile(admin_q_db as *mut u32, 2) }
loop {
let status = admin_queue.cq[1].read();
if status.status != 0 {
unsafe { write_volatile((admin_q_db + 0x4) as *mut u32, 2) }
break;
}
}
let mut cmd = NvmeCreateCq::new();
cmd.opcode = 0x05;
cmd.command_id = 0x3;
cmd.nsid = 1;
cmd.prp1 = admin_queue.cq_pa as u64;
cmd.cqid = 1;
cmd.qsize = 1023;
cmd.cq_flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
let common_cmd = unsafe { core::mem::transmute(cmd) };
admin_queue.sq[2].write(common_cmd);
admin_queue.sq_tail += 1;
unsafe { write_volatile(admin_q_db as *mut u32, 3) }
loop {
let status = admin_queue.cq[2].read();
if status.status != 0 {
unsafe { write_volatile((admin_q_db + 0x4) as *mut u32, 3) }
break;
}
}
let mut cmd = NvmeCreateSq::new();
cmd.opcode = 0x01;
cmd.command_id = 0x4;
cmd.nsid = 1;
cmd.prp1 = admin_queue.sq_pa as u64;
cmd.sqid = 1;
cmd.qsize = 1023;
cmd.sq_flags = 0x1;
cmd.cqid = 0x1;
let common_cmd = unsafe { core::mem::transmute(cmd) };
admin_queue.sq[3].write(common_cmd);
admin_queue.sq_tail += 1;
unsafe { write_volatile(admin_q_db as *mut u32, 4) }
loop {
let status = admin_queue.cq[3].read();
if status.status != 0 {
unsafe { write_volatile((admin_q_db + 0x4) as *mut u32, 4) }
break;
}
}
}
}
impl BlockScheme for NvmeInterface {
fn read_block(&self, block_id: usize, read_buf: &mut [u8]) -> DeviceResult {
let io_queue = self.io_queues[0].lock();
let db_offset = io_queue.db_offset;
let mut admin_queue = self.admin_queue.lock();
let bar = self.bar;
let dbs = bar + NVME_REG_DBS;
let ptr = read_buf.as_mut_ptr();
let addr = virt_to_phys(ptr as usize);
let mut cmd = NvmeRWCommand::new_read_command();
cmd.nsid = 1;
cmd.prp1 = addr as u64;
cmd.command_id = 101;
cmd.length = 1;
cmd.slba = block_id as u64;
let common_cmd = unsafe { core::mem::transmute(cmd) };
let tail = admin_queue.sq_tail;
admin_queue.sq[tail].write(common_cmd);
admin_queue.sq_tail += 1;
unsafe { write_volatile((dbs + db_offset) as *mut u32, (tail + 1) as u32) }
loop {
let status = admin_queue.cq[tail].read();
if status.status != 0 {
unsafe { write_volatile((dbs + db_offset + 0x4) as *mut u32, (tail + 1) as u32) }
break;
}
}
Ok(())
}
fn write_block(&self, block_id: usize, write_buf: &[u8]) -> DeviceResult {
let io_queue = self.io_queues[0].lock();
let db_offset = io_queue.db_offset;
let mut admin_queue = self.admin_queue.lock();
let bar = self.bar;
let dbs = bar + NVME_REG_DBS;
let ptr = write_buf.as_ptr();
let addr = virt_to_phys(ptr as usize);
let mut cmd = NvmeRWCommand::new_write_command();
cmd.nsid = 1;
cmd.prp1 = addr as u64;
cmd.length = 1;
cmd.command_id = 100;
cmd.slba = block_id as u64;
let common_cmd = unsafe { core::mem::transmute(cmd) };
let mut tail = admin_queue.sq_tail;
if tail > 1023 {
tail = 0;
}
admin_queue.sq[tail].write(common_cmd);
admin_queue.sq_tail += 1;
unsafe { write_volatile((dbs + db_offset) as *mut u32, (tail + 1) as u32) }
loop {
let status = admin_queue.cq[tail].read();
if status.status != 0 {
unsafe { write_volatile((dbs + db_offset + 0x4) as *mut u32, (tail + 1) as u32) }
break;
}
}
Ok(())
}
fn flush(&self) -> DeviceResult {
Ok(())
}
}
impl Scheme for NvmeInterface {
fn name(&self) -> &str {
"nvme"
}
fn handle_irq(&self, irq: usize) {
warn!("nvme device irq {}", irq);
}
}
#[repr(C)]
#[derive(Debug, Clone, Copy, Default)]
pub struct NvmeCommonCommand {
opcode: u8,
flags: u8,
command_id: u16,
nsid: u32,
cdw2: [u32; 2],
metadata: u64,
prp1: u64,
prp2: u64,
cdw10: u32,
cdw11: u32,
cdw12: u32,
cdw13: u32,
cdw14: u32,
cdw15: u32,
}
impl NvmeCommonCommand {
pub fn new() -> Self {
Self {
opcode: 0,
flags: 0,
command_id: 0,
nsid: 0,
cdw2: [0; 2],
metadata: 0,
prp1: 0,
prp2: 0,
cdw10: 0,
cdw11: 0,
cdw12: 0,
cdw13: 0,
cdw14: 0,
cdw15: 0,
}
}
}
#[repr(C)]
#[derive(Debug, Clone, Copy, Default)]
pub struct NvmeIdentify {
opcode: u8,
flags: u8,
command_id: u16,
nsid: u32,
rsvd2: [u64; 2],
prp1: u64,
prp2: u64,
cns: u8,
rsvd3: u8,
ctrlid: u16,
rsvd11: [u8; 3],
csi: u8,
rsvd12: [u32; 4],
}
impl NvmeIdentify {
pub fn new() -> Self {
Self {
opcode: 0x06,
flags: 0,
command_id: 0x1,
nsid: 1,
rsvd2: [0; 2],
prp1: 0,
prp2: 0,
cns: 1,
rsvd3: 0,
ctrlid: 0,
rsvd11: [0; 3],
csi: 0,
rsvd12: [0; 4],
}
}
}
#[repr(C)]
#[derive(Debug, Clone, Copy, Default)]
pub struct NvmeCreateCq {
pub opcode: u8,
pub flags: u8,
pub command_id: u16,
pub nsid: u32,
pub rsvd1: [u32; 4],
pub prp1: u64,
pub rsvd8: u64,
pub cqid: u16,
pub qsize: u16,
pub cq_flags: u16,
pub irq_vector: u16,
pub rsvd12: [u32; 4],
}
impl NvmeCreateCq {
fn new() -> Self {
Self {
opcode: 0x05,
flags: 0,
command_id: 0,
nsid: 0,
rsvd1: [0; 4],
prp1: 0,
rsvd8: 0,
cqid: 0,
qsize: 0,
cq_flags: 0,
irq_vector: 0,
rsvd12: [0; 4],
}
}
}
#[repr(C)]
#[derive(Debug, Clone, Copy, Default)]
pub struct NvmeCreateSq {
pub opcode: u8,
pub flags: u8,
pub command_id: u16,
pub nsid: u32,
pub rsvd1: [u32; 4],
pub prp1: u64,
pub rsvd8: u64,
pub sqid: u16,
pub qsize: u16,
pub sq_flags: u16,
pub cqid: u16,
pub rsvd12: [u32; 4],
}
impl NvmeCreateSq {
fn new() -> Self {
Self {
opcode: 0x01,
flags: 0,
command_id: 0,
nsid: 0,
rsvd1: [0; 4],
prp1: 0,
rsvd8: 0,
sqid: 0,
qsize: 0,
sq_flags: 0,
cqid: 0,
rsvd12: [0; 4],
}
}
}
#[repr(C)]
#[derive(Copy, Clone, Debug, Default)]
pub struct NvmeRWCommand {
pub opcode: u8,
pub flags: u8,
pub command_id: u16,
pub nsid: u32,
pub rsvd2: u64,
pub metadata: u64,
pub prp1: u64,
pub prp2: u64,
pub slba: u64,
pub length: u16,
pub control: u16,
pub dsmgmt: u32,
pub reftag: u32,
pub apptag: u16,
pub appmask: u16,
}
impl NvmeRWCommand {
pub fn new_write_command() -> Self {
Self {
opcode: 0x01,
flags: 0,
command_id: 0,
nsid: 0,
rsvd2: 0,
metadata: 0,
prp1: 0,
prp2: 0,
slba: 0,
length: 0,
control: 0,
dsmgmt: 0,
reftag: 0,
apptag: 0,
appmask: 0,
}
}
pub fn new_read_command() -> Self {
Self {
opcode: 0x02,
flags: 0,
command_id: 0,
nsid: 0,
rsvd2: 0,
metadata: 0,
prp1: 0,
prp2: 0,
slba: 0,
length: 0,
control: 0,
dsmgmt: 0,
reftag: 0,
apptag: 0,
appmask: 0,
}
}
}
#[repr(C)]
#[derive(Debug, Copy, Clone, Default)]
pub struct NvmeCompletion {
pub result: u64,
pub sq_head: u16,
pub sq_id: u16,
pub command_id: u16,
pub status: u16,
}
pub const NVME_REG_CAP: usize = 0x0000;
pub const NVME_REG_VS: usize = 0x0008;
pub const NVME_REG_INTMS: usize = 0x000c;
pub const NVME_REG_INTMC: usize = 0x0010;
pub const NVME_REG_CC: usize = 0x0014;
pub const NVME_REG_CSTS: usize = 0x001c;
pub const NVME_REG_NSSR: usize = 0x0020;
pub const NVME_REG_AQA: usize = 0x0024;
pub const NVME_REG_ASQ: usize = 0x0028;
pub const NVME_REG_ACQ: usize = 0x0030;
pub const NVME_REG_CMBLOC: usize = 0x0038;
pub const NVME_REG_CMBSZ: usize = 0x003c;
pub const NVME_REG_BPINFO: usize = 0x0040;
pub const NVME_REG_BPRSEL: usize = 0x0044;
pub const NVME_REG_BPMBL: usize = 0x0048;
pub const NVME_REG_CMBMSC: usize = 0x0050;
pub const NVME_REG_CRTO: usize = 0x0068;
pub const NVME_REG_PMRCAP: usize = 0x0e00;
pub const NVME_REG_PMRCTL: usize = 0x0e04;
pub const NVME_REG_PMRSTS: usize = 0x0e08;
pub const NVME_REG_PMREBS: usize = 0x0e0c;
pub const NVME_REG_PMRSWTP: usize = 0x0e10;
pub const NVME_REG_DBS: usize = 0x1000;
pub const NVME_CC_ENABLE: u32 = 1 << 0;
pub const NVME_CC_CSS_NVM: u32 = 0 << 4;
pub const NVME_CC_MPS_SHIFT: u32 = 7;
pub const NVME_CC_ARB_RR: u32 = 0 << 11;
pub const NVME_CC_ARB_WRRU: u32 = 1 << 11;
pub const NVME_CC_ARB_VS: u32 = 7 << 11;
pub const NVME_CC_SHN_NONE: u32 = 0 << 14;
pub const NVME_CC_SHN_NORMAL: u32 = 1 << 14;
pub const NVME_CC_SHN_ABRUPT: u32 = 2 << 14;
pub const NVME_CC_IOSQES: u32 = 6 << 16;
pub const NVME_CC_IOCQES: u32 = 4 << 20;
pub const NVME_CSTS_RDY: u32 = 1 << 0;
pub const NVME_CSTS_CFS: u32 = 1 << 1;
pub const NVME_CSTS_SHST_NORMAL: u32 = 0 << 2;
pub const NVME_CSTS_SHST_OCCUR: u32 = 1 << 2;
pub const NVME_CSTS_SHST_CMPLT: u32 = 2 << 2;
pub const NVME_QUEUE_PHYS_CONTIG: u16 = 1 << 0;
pub const NVME_CQ_IRQ_ENABLED: u16 = 1 << 1;
pub const NVME_SQ_PRIO_URGENT: u16 = 0 << 1;
pub const NVME_SQ_PRIO_HIGH: u16 = 1 << 1;
pub const NVME_SQ_PRIO_MEDIUM: u16 = 2 << 1;
pub const NVME_SQ_PRIO_LOW: u16 = 3 << 1;
pub const NVME_FEAT_ARBITRATION: u32 = 0x01;
pub const NVME_FEAT_POWER_MGMT: u32 = 0x02;
pub const NVME_FEAT_LBA_RANGE: u32 = 0x03;
pub const NVME_FEAT_TEMP_THRESH: u32 = 0x04;
pub const NVME_FEAT_ERR_RECOVERY: u32 = 0x05;
pub const NVME_FEAT_VOLATILE_WC: u32 = 0x06;
pub const NVME_FEAT_NUM_QUEUES: u32 = 0x07;
pub const NVME_FEAT_IRQ_COALESCE: u32 = 0x08;
pub const NVME_FEAT_IRQ_CONFIG: u32 = 0x09;
pub const NVME_FEAT_WRITE_ATOMIC: u32 = 0x0a;
pub const NVME_FEAT_ASYNC_EVENT: u32 = 0x0b;
pub const NVME_FEAT_SW_PROGRESS: u32 = 0x0c;